1. Technical Field
The present invention relates to semiconductor structures, and more particularly, to semiconductor structures with reduced gate-source/drain capacitances.
2. Related Art
A typical semiconductor transistor comprises a channel region and first and second source/drain (S/D) regions formed in a semiconductor layer, wherein the channel region is disposed between the first and second S/D regions. The typical semiconductor transistor further comprises a gate stack (that includes a gate dielectric region directly on top the channel region and a gate region on top of the gate dielectric region) directly above the channel region. In addition, the typical semiconductor transistor further comprises first and second gate spacers on opposing side walls of the gate stack so as to define the first and second S/D regions, respectively. The capacitance between the gate region and the first S/D region has several components one of which is defined by a path from the gate region to the first S/D region through the first gate spacer. This capacitance component is usually referred to as the out-fringing capacitance. For example, the out-fringing capacitance between the gate region and the second S/D region is defined by a path from the gate region to the second S/D region through the second gate spacer.
It is desirable to eliminate the out-fringing capacitances between the gate region and the first and second S/D regions in order to increase transistor performance or to reduce transistor switching time. Therefore, there is a need for a novel transistor structure (and a method for forming the same) that does not have the out-fringing capacitances between the gate region and the first and second S/D regions.